The present disclosure relates to a circuit for control of phases of clock signals, and more specifically, to a phase rotator that allows for operation at high frequencies and power savings at lower frequencies.
Phase rotators are important parts of clock subsystems in data processing and communications systems. The predominant architecture for phase rotators use current-mode logic (CML) structures with quadrature clock sets of I, Q in which phases 0° (called +I, I, or I+), 90° or
  π  2radians (called +Q, Q, or Q+), 180° or π radians (called −I, Ī, or I−), and 270° or
      3    ⁢                  ⁢    π    2radians (called −Q, Q, or Q−). Weighting currents are applied to the four phases to produce a phase shifted signal, initially as a differential output current. Load resistors/impedances are connected to each part of the differential output current to convert the output to a differential output voltage. This architecture has the advantage of relative simplicity, but as speeds increase, CML-based phase rotators have ever-higher power demands-producing ever-lower efficiencies. While various strategies can be employed to increase usable data rates while mitigating power consumption, alternatives to CML-based phase rotators with higher efficiency and lower power requirements are desirable for use with emerging high-frequency clock data recovery (CDR) systems.